RISC-V Day Tokyo 2020, which was scheduled to be held at Nikkei Hall (610 seats) on November 05, 2020, will be held in a multi-track format over two days from November 05-06, with an online conference as the main focus.
It was a good thing that we were able to meet the selection criteria for the Nikkei Hall and secure a physical location for the event. Just as I was about to do so, the coronavirus gave me a blank slate with or without warning.
The ongoing measures to prevent corona epidemics are an administrative problem that affects the lives of the people and the economy. For the government of any country, it is inevitable that it will be influenced by politics. As of February, it was clear that the holding of RISC-V Day Tokyo 2020 would be made possible by the organizers and participants having a certain proactive policy on the issue of coronavirus epidemic control.
Since the end of last year, I’ve been discussing with RISC-V Foundation / International member companies and Japanese speakers from multinational member companies rather than Japanese members. I understood that the group had an extremely keen awareness of the current situation, innovative ideas, and concrete planning ability. The Nikkei Hall reservation is still preserved and I think we can symbolically use the empty hall that seats 610 people.
The role that RISC-V Day Tokyo 2020 is trying to play is as follows
Overview of RISC-V commercialization at home and abroad: Confirmation of the status of RISC-V-based chip products, IP and software.
Introduction of domestic and international RISC-V research and development: 2.
Introduction of domestic and international RISC-V hardware and software integrators: 3.
RISC-V adoption at domestic and overseas semiconductor companies (IDMs): 4.
(1) Japan IDM widely acknowledged that it offers advantages over other alternatives in terms of long-term cost, flexibility and scalability.
(2) Looking at the wide range of developments such as nVidia’s GPGPU, Samsung, Qualcomm’s 5G mobile chip, Western Digital’s storage, and Chinese wearables, it is understood that RISC-V’s tool chain, OS, and middleware are sustainable technologies supported by open source software (OSS).
(3) Japanese IDMs are evaluating RISC-V’s open RTL and paid IP. There is a clear direction to move forward with the development. Like Samsung’s 5G chip development, planning, design, prototyping, and mass-production prototyping require several years of time. After the final product is completed and the press release is made, it takes time to see tangible results. IDM Japan often targets mission-critical applications, and the V-shaped development process and planning, design, and prototyping take a lot of time.
(4) Japan IDM’s concern is that if it moves ahead from other options, it will incur software porting costs. I’d like to know how much real effort will be required to adopt such CPU IP when the focus is on application and product development, as well as middleware and libraries.
Western Digital, Qualcomm, Samsung, NVIDIA, Huawei, etc. are examples of this. As much as possible, you need to be specific about your successful experience in your talks and exhibits.
RISC-V adoption at Japanese startups: Many Japanese startups have already started RISC-V design and have prototypes that are close to commercialization.
The following are pre-announcement. The proposals are sought in the following areas:
① SoC design based on RISC-V core
② RISC-V core design such as low power and performance enhancement
③ RISC-V software development tools such as compiler, debugger, OS, profiler
④ RTL simulator, design tools such as DFT, open source EDA
⑤ Domain specific architecture such as AI, IoT, autonomous driving
⑥ RISC-V application library standard interface
⑦ Use of RISC-V for education
Submitted on May 30, 2020.
Notice: July 30, 2020.