RISC-V Alliance Japan

Menu
  • Events
    • RISC-V Days Tokyo 2020
    • RISC-V Day Vietnam 2020
    • RISC-V Day Tokyo 2019
  • RISC-V International
  • Facebook
  • 日本語日本語

RISC-V Days Tokyo 2021 Spring Virtual Booths Details


 

Ariel IoT SoC Development Platform Featuring Andes N25F RISC-V Core Demo PDF Demo Video Go to Demo

Booth Opens:
4/22 10:00-16:00
4/23 10:00-16:00

Booth Attendants
Florian Wohlrab
Head of Sales for EMEA and Japan at Andes Technology

Contact Andes
Andes Technology Corporation is a world-class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve the rapidly growing global embedded system applications. The company delivers superior low power CPU cores, including the comprehensive RISC-V V5 family of processor IPs, with integrated development environment and associated software/hardware solutions for efficient SoC design. Up to the end of 2019, the cumulative volume of Andes-Embedded™ SoCs has surpassed the 5-billion mark. Andes Technology’s comprehensive CPU line includes extensible entry-level, mid-range and high-end families. For more information, please visit www.andestech.com

 


 

SHC RISC-V Demo: Securely Connect Andes N22 RISC-V to Amazon AWS IoT Cloud with Root of Trust Chip Demo PDF Demo Video Go the Demo

Booth Opens:
4/22 14:00-16:00
4/23 14:00-16:00

Booth Attendant
Hoan Huynh
SH Consulting
Vietnam

Contact SH Consulting

This demo shows a Secure IoT solution using a Corvette-F1 board, evaluation kit with full support for the 32-bit AndesCore N25 and the AndeShape AE250 Platform, runs Amazon FreeRTOS, which is an open source operating system for microcontrollers from Amazon Web Services (AWS). It uses an ESP32-WROOM board as an external Wi-fi module. ATECC608A-MAHDA chip is integrated such as Trusted Platform Module (TPM) to provide hardware-based endpoint device security. This integration ensures the private key used to establish device identity can be securely stored in tamper-proof hardware devices to prevent it from being taken out of the devices for impersonation and other malicious activities.

In IoT solution deployments, it is important to check the identity of the device that is communicating with the messaging gateway. For the first time running demo, TPM will generate key pairs for the devices, which are then used to authenticate and encrypt the traffic. The keys are generated inside the TPM itself and are thereby protected from being retrieved by external programs. In fact, even without harnessing the capabilities of a hardware root of trust and secure boot, the TPM is also valuable just as a hardware key store. The private keys are protected by the hardware and offer far better protection than a software key. This integration uses the PKCS#11 protocol as the interface to the TPM.

After generating key pairs, this demo uses the FreeRTOS MQTT library to connect to the AWS Cloud and then periodically publish messages to an MQTT topic hosted by the AWS IoT MQTT broker. A specific Android application developed by SHC also uses this topic to communicate with Corvette-F1 board to control its on-board LEDs.


About RISC-V Association

RISC-V-logo-figonly-mod-2

RISC-V Association is an association among RISC-V Foundation member companies. RISC-V Foundation defines Member Sponsored Events and Meetups as regional efforts and RISC-V Association supports these events. Presently Software Hardware Consulting handles business ends of this activity.

Recent Posts

  • IoT MCU pioneer Espressif adopts RISC-V in Entire Fleet of new ESP32 Introduced in 2021
  • Expressif has started sample distribution of ESP32-C2 with built-in RISC-V MCU, 2.4GHz Wi-Fi, and BluetoothLE 5.0!
  • nVidia, ARM, RISC-V and RISC-V Days Tokyo 2020
  • The program of RISC-V Days Tokyo 2020 to be held from Thursday, November 5th to Friday, November 6th has been released.
  • Successful RISC-V Days Vietnam 2020! Full Steam Ahead to Tokyo Days 2020 November 5-6.
  • Register for RISC-V Global Forum for the latest on RISC-V!
  • RISC-V Days Tokyo Online 2020: November 5, 2020 (Thursday)  – 6, 2020 (Friday)
  • UltraSoC & NSITEXE Webinar Information July 29th (Wed) 17:00-18:00 Japan TIme Zone
  • Happy 10th Birthday RISC-V!
  • RISC-V Day Tokyo 2020 on November 05-06 will be held as an online conference

Archives

  • February 2021 (2)
  • October 2020 (2)
  • September 2020 (1)
  • August 2020 (2)
  • July 2020 (1)
  • May 2020 (1)
  • April 2020 (1)
  • November 2019 (3)
  • October 2019 (15)
  • September 2019 (5)
  • August 2019 (1)
  • June 2019 (1)
  • Events
  • RISC-V International
  • Facebook
Privacy Policy
© 2021-2021 RISC-V Alliance Japan